Optimal and Power Aware BIST for Delay Testing of System-On-Chip

Test engineering for fault tolerant VLSI systems is encumbered with optimization requisites for hardware overhead, test power and test time. The high level quality of these complex high-speed VLSI circuits can be assured only through delay testing, which involves checking for accurate temporal behavior. In the present paper, a data-path based built-in test pattern generator (TPG) that generates iterative pseudo-exhaustive two-patterns (IPET) for parallel delay testing of modules with different input cone capacities is implemented. Further, in the present study a CMOS implementation of low power architecture (LPA) for scan based built-in self test (BIST) for delay testing and combinational testing is carried out. This reduces test power dissipation in the circuit under test (CUT). Experimental results and comparisons with pre-existing methods prove the reduction in hardware overhead and test-time.